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HM621664H/HM621864H Series
65536-word x 16/18-bit High Speed CMOS Static RAM
Description
The HM621664H/HM621864H is an asynchronous high speed static RAM organized as 64-kword x 16/18bit. It realize high speed access time (20/25 ns) with employing 0.8 m CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM621664H/HM621864H is packaged in 400-mil 44-pin SOJ for high density surface mounting.
Features
* Single 5 V supply: 5 V 10% * Access time 20/25 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible All inputs and outputs * 400-mil 44-pin SOJ package * Center VCC and VSS type pinout
Ordering Information
Type No. HM621664HJP-20 HM621664HJP-25 HM621664HLJP-20 HM621664HLJP-25 HM621864HJP-20 HM621864HJP-25 HM621864HLJP-20 HM621864HLJP-25 Access Time 20 ns 25 ns 20 ns 25 ns 20 ns 25 ns 20 ns 25 ns Package 400-mil 44-pin plastic SOJ (CP-44D)
HM621664H/HM621864H Series
Pin Arrangement
HM621664HJP
A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (Top View) A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 I/O9 WE A15 A14 A13 A12
HM621864HJP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top View) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O18 I/O17 I/O16 I/O15 VSS VCC I/O14 I/O13 I/O12 I/O11 I/O10 NC A8 A9 A10 A11
Pin Description
Pin Name HM621664H A0 - A15 I/O1 - I/O8 I/O9 - I/O16 CS LB UB WE OE VCC VSS NC HM621864H A0 - A15 I/O1 - I/O9 I/O10 - I/O18 CS LB UB WE OE VCC VSS NC Function Address Input/output (lower byte) Input/output (upper byte) Chip select Lower byte select Upper byte select Write enable Output enable Power supply Ground No connection
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HM621664H/HM621864H Series
Block Diagram
A4 A3 A2 A1 A0 A7 A6 A5
VCC Row Decoder Memory Matrix 256 rows x 256 x 16/18 columns VSS
CS I/O1 . . . I/O8/9 I/O9/10 . . . I/O16/18 WE CS LB UB Column I/O Input Data Control Column Decoder CS
A12 A11 A10 A15 A14 A13 A9 A8
OE
CS
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5
*2 *1
Unit V V W C C C
to V CC + 0.5
*3
1.0 / 1.5 0 to +70
-55 to +125 -10 to +85
Notes: 1. -2.5 V for pulse width (under shoot) 10 ns 2. at still air condition 3. at air flow 1.0 m/s
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HM621664H/HM621864H Series
Function Table
CS OE WE LB UB VCC Current H L L L L L L L L L X H L L L L X X X X X H H H H H L L L L X X L L H H L L H H X X L H L H L H L H I SB , I SB1 I CC I CC I CC I CC I CC I CC I CC I CC I CC I/O (Lower Byte) High-Z High-Z Output Output High-Z High-Z Input Input High-Z High-Z I/O (Upper Byte) Ref. Cycle High-Z High-Z Output High-Z Output High-Z Input High-Z Input High-Z -- Read cycle Read cycle Read cycle -- Write cycle Write cycle Write cycle --
Note: X: H or L
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage
*2
Symbol VCC VSS
Min 4.5 0 2.2 -0.5
*1
Typ 5.0 0 -- --
Max 5.5 0 VCC + 0.5 0.8
Unit V V V V
Input voltage
VIH VIL
Notes: 1. -2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
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HM621664H/HM621864H Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
Parameter Symbol Min -- -- -- Typ*1 -- -- 160 Max 2 2 220 Unit Test Conditions A A mA Vin = VSS to V CC VI/O = VSS to V CC 20 ns cycle CS = VIL, Iout = 0 mA Other inputs = VIH/V IL CS = VIH, Other inputs = VIH/V IL Note Input leakage current |ILI| Output leakage current Operating power supply current |ILO | I CC
-- Standby power supply current I SB --
145 50
200 90
mA mA
25 ns cycle 20 ns cycle
-- Standby power supply current (1) I SB1 --
40 --
85 2
mA mA
25 ns cycle VCC CS V CC - 0.2 V, 0 V Vin 0.2 V or VCC Vin V CC - 0.2 V L-version I OL = 8 mA I OH = -4 mA
-- Output voltage VOL VOH Note: -- 2.4
-- -- --
0.2 0.4 --
mA V V
1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed.
Capacitance (Ta = 25C, f = 1.0 MHz)*1
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 6 8 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V
1. This parameter is sampled and not 100% tested.
5
HM621664H/HM621864H Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: VSS to 3.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5 V Output load: See figures
+5 V +5 V
480 Dout 255 30 pF*1 Dout 255
480
5 pF*1
Output Load (A) Note: 1. Including scope and jig
Output Load (B) (for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ, tLBHZ, tUBHZ, tWHZ, and tOW)
Read Cycle
HM621664H/HM621864H -20 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Byte select to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Byte select to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Byte deselect to output in high-Z Note: Symbol t RC t AA t ACS t OE t LB, tUB t OH t CLZ t OLZ t LBLZ, t UBLZ t CHZ t OHZ t LBHZ, t UBHZ Min 20 -- -- -- -- 5 3 1 1 -- -- -- Max -- 20 20 10 10 -- -- -- -- 7 7 7 -25 Min 25 -- -- -- -- 5 3 1 1 -- -- -- Max -- 25 25 12 12 -- -- -- -- 7 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 Note
1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested.
6
HM621664H/HM621864H Series
Read Timing Waveform (WE = VIH)
t RC
Address
Valid address t AA t ACS t OH t CHZ
CS t OE OE t LB , t UB t LBHZ , t UBHZ t OHZ
LB, UB t OLZ , t LBLZ , t UBLZ t CLZ Dout High Impedance *1 Valid data
Note: 1. When CS, OE and LB are low, Dout (lower byte) is low impedance. When CS, OE and UB are low, Dout (upper byte) is low impedance.
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HM621664H/HM621864H Series
Write Cycle
HM621664H/HM621864H -20 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Byte select to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Write enable to output in high-Z Notes: 1. 2. 3. 4. Symbol t WC t AW t CW t WP t LBW, t UBW t AS t WR t DW t DH t OW t WHZ Min 20 15 12 12 12 0 0 10 0 3 -- Max -- -- -- -- -- -- -- -- -- -- 7 -25 Min 25 20 12 12 12 0 0 10 0 3 -- Max -- -- -- -- -- -- -- -- -- -- 7 Unit Notes ns ns ns ns ns ns ns ns ns ns ns 4 4 2 3
A write occurs during the overlap of low CS, low WE and low LB or low UB. t AS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. t WR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. Transition is measured 200 mV from high impedance state's voltage with Load (B). This parameter is sampled and not 100% tested.
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HM621664H/HM621864H Series
Write Timing Waveform (1) (WE Controlled)
t WC Address Valid address t AW t AS WE
*1
t WR t WP
t CW CS
t LBW , t UBW UB, LB t WHZ Dout t DW Din
*2
t OW
t DH
*2
Valid data
Notes: 1. WE must be high during address transition except when the device is disabled with CS, LB or UB. 2. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them.
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HM621664H/HM621864H Series
Write Timing Waveform (2) (CS Controlled)
t WC Address Valid address t AW t WP WE t CW CS t AS t LBW , t ULB LB, UB t DW Din
*1
t WR
t DH
*1
Valid data
Note: 1. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state.
10
HM621664H/HM621864H Series
Write Timing Waveform (3) (LB, UB Controlled)
t WC Address Valid address t AW t WP WE t CW CS t LBW , t UBW LB, UB t AS t DW
*1
t WR
t DH
*1
Din
Valid data
Note: 1. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state.
11
HM621664H/HM621864H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
This characteristics is guaranteed only for L-version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions VCC CS VCC - 0.2 V, VCC Vin V CC - 0.2 V or 0 V Vin 0.2 V
Data retention current
I CCDR
-- 0 5
2 -- --
80*1 -- --
A ns ms
Chip deselect to data retention time t CDR Operation recovery time Note: 1. V CC = 3.0 V tR
Low V CC Data Retention Timing Waveform
t CDR V CC 4.5 V Data retention mode tR
2.2 V V DR CS 0V CS > VCC - 0.2 V
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HM621664H/HM621864H Series
Package Dimension
HM621664HJP/HLJP, HM621864HJP/HLJP Series (CP-44D)
28.33 28.90 Max 44 23 10.16 0.13 11.18 0.13 Unit: mm
1.30 Max
0.43 0.10 0.10
1.27
0.80
9.40 0.25
2.65 0.12
0.74
3.50 0.26
1
22
+0.25 -0.17
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